Barrel shifter for a microprocessor

ABSTRACT

A 2N bit right only barrel shifter for a microprocessor comprising upper and lower N bit shifter portions. A N bit input is put in the upper portion. An X bit right shift of the N bit number yields the results in the N bit upper portion and the result of an N-X bit left shift in the lower portion. The N bit shifter is comprised of a Log 2 N stage multiplexer where in each successive stage of the multiplexer adds 2 x  additional bits where x increments from 0 to (Log 2 N-1).

CROSS REFERENCE TO RELATED APPLICATION(S)

This application claims priority to provisional application No. 60/572,238 filed May 19, 2004, entitled “Microprocessor Architecture,” hereby incorporated by reference in its entirety.

FIELD OF THE INVENTION

This invention relates generally to microprocessor architecture and more specifically to a design for a rotation and shifting logic element of a microprocessor.

BACKGROUND OF THE INVENTION

Data within a computer or other digital circuit is typically organized into one or more standard data sizes, referred to as data words. For example, a very common data word size contains 32 bits of binary data (zeros and ones). The size of the data word affects precision and/or resolution of the information contained within the digital circuit, with larger data sizes allowing greater precision and/or resolution because they can represent more values. Larger data words, however, require larger digital circuits to manipulate the data, leading to greater cost and complexity. In addition to manipulating data of a maximum data size, many digital circuits also allow data of smaller, evenly divided sizes to be manipulated. For example, a digital circuit with a maximum data word size of 32 bits might also manipulate 8-bit or 16-bit data. A data operand that is half the size of the maximum data word is typically called a half-word. When the extra precision is not required, manipulating smaller data operands may provide advantages such as requiring less memory to store the data or allowing multiple data operands to be manipulated simultaneously by the same circuit.

Two manipulation operations that have proven to be useful when working with digital data are rotation and shifting. The bits of data within a data word are arranged in a fixed order, typically from most significant bit (MSB) in the leftmost position to least significant bit (LSB) in the rightmost position. The rotation operation takes a data word as an input operand and rearranges the order of the bits within that data word by moving bit values to the left or the right by a number of bit positions which may be fixed or may be specified by a second input operand. When rotating to the left, bit values that are moved past the MSB bit position are inserted into the right side bit positions which have been left vacant by the other bits being moved to the left. When rotating to the right, bits that are moved past the LSB bit position are inserted into the left side bit positions in the same manner. For example, consider a 32-bit data word:

-   -   0101 0001 0000 0000 0000 0000 1010 1110         An instruction to rotate this data word left by four bits         results in the new value:     -   0001 0000 0000 0000 0000 1010 1110 0101         Since the values of the bits that are being rotated out the top         or bottom of the data word are wrapped around and inserted at         the other end of the data word, no bit values are lost.

The second operation, shifting, also takes a data word as an input operand and rearranges the order of the bits within that data word by moving bit values to the left or the right by a number of bit positions which may be fixed or may be specified by a second input operand. A shift operation, however, discards the bit values that are moved past the MSB or LSB bit positions. The bit positions that are left empty by the shift operation are filled with a fixed value, most commonly either with all 0s or all 1s. As an example, consider a 32-bit data word:

-   -   0101 0001 0000 0000 0000 0000 1010 1110         An instruction to shift this word left by four bits results in         the new value:     -   0001 0000 0000 0000 0000 1010 1110 0000         It is also common when shifting to the right to use the value of         the input at the MSB bit position to fill the bit positions that         are left empty. For signed binary numbers, this has the property         of ensuring that the number keeps the same sign.

As noted above, shifting and rotation are manipulation functions frequently performed in the execution stage of a microprocessor pipeline. Most microprocessors employ a logic unit known as a barrel shifter for effecting bitwise shifts of binary numbers. Barrel shifters permit shifting of an N bit word either to the left or to the right by 0, 1, 2, . . . N-1 bits. As noted above, a typical 32-bit barrel shifter will consist of a series of multiplexers. Referring to FIG. 1, a conventional right and left barrel shifter structure 100 is shown. In order to permit bi-directional shifting, duplicative hardware is used in parallel, with one side performing leftward shifts and the other performing rightward shifts. A single 5-bit control line will tell each stage of the multiplexer to effect a shift. In this manner, any combination of shifts between 0 and 31 bits may be effected by enabling various combinations of the 5 multiplexer stages. For example, a nine-bit shift would have a control signal of 01001, enabling the 1^(st) and the 4^(th) multiplexers while disabling the others. One of the parallel shifters will perform a right directional shift while the other performs a left directional shift. Selection logic at the output of the last of each parallel multiplexer will select the appropriate result.

The conventional barrel shifter is effective at shifting, however, it is a less than ideal solution because the redundant hardware structure occupies extra space on the chip, consumes additional power and complicates the hardware design. The hardware complexity of this 32-bit barrel shifter can be characterised by the number of 2:1 multiplexers required to implement its functionalities. In this case, 5 stages each of 32 2:1 multiplexers are required resulting in 160 2:1 multiplexers. In general, the number of 2:1 multiplexers required to implement an N-bit barrel shifter, where N is a positive integer and a power of 2, is N log₂(N). As noted above, a typical processor needs two such barrel shifters to implement both left and right shifts. In the case of a 32-bit processor, this requires 320 2:1 multiplexers. With two such barrel shifters working in parallel on the same input data, the rotation operation can also be implemented with additional logic to compute the effective shift distance required in each shifter and then combining the results of the shift operations. This can be illustrated by way of an example of rotating a 32-bit number to the right by 4 bit positions. In this case, the right shifter has to shift the input data by 4 bit positions and the left shifter has to shift the input data by 28 bit positions. The rotation result can then be obtained by combining the two shifter outputs using the bitwise logical OR operation. In general, to rotate the input data by D bit positions, where D is a non-negative integer less than the data word length N, a shift distance of D is applied to the shifter of the same direction as the rotation and a shift distance of (N-D) is applied to the shifter of the opposite direction. In a processor that supports negative shift distance, further additional logic is required to compute the absolute value of a negative shift distance and apply it to the shifter with a shift direction opposite to the specified one.

It should be appreciated that the description herein of various advantages and disadvantages associated with known apparatus, methods, and materials is not intended to limit the scope of the invention to their exclusion. Indeed, various embodiments of the invention may include one or more of the known apparatus, methods, and materials without suffering from their disadvantages.

As background to the techniques discussed herein, the following references are incorporated herein by reference: U.S. Pat. No. 6,862,563 issued Mar. 1, 2005 entitled “Method And Apparatus For Managing The Configuration And Functionality Of A Semiconductor Design” (Hakewill et al.); U.S. Ser. No. 10/423,745 filed Apr. 25, 2003, entitled “Apparatus and Method for Managing Integrated Circuit Designs”; and U.S. Ser. No. 10/651,560 filed Aug. 29, 2003, entitled “Improved Computerized Extension Apparatus and Methods”, all assigned to the assignee of the present invention.

SUMMARY OF THE INVENTION

Thus, there exists a need for a barrel shifter that ameliorates and/or eliminates one or more of the above noted problems. In particular, there exists a need for a barrel shifter with reduced power consumption, improved performance and/or reduction of silicon footprint as compared with conventional barrel shifter devices.

In various embodiments, this is accomplished through a microprocessor architecture that utilizes a barrel shifter characterized by reduction in complexity, reduced power consumption and enhanced capability over conventional barrel shifter designs. In various exemplary embodiments, the barrel shifter comprises a 64 bit right-shifting barrel shifter capable of right and left directional shifts of a 32 bit input with positive or negative shift distance. In various exemplary embodiments, a right shift of n bits (n<32) is equivalent to a negative left shift of 32-n bits, and a left shift by n bits is equivalent to a negative right shift of 32-n bits. In various exemplary embodiments, the barrel shifter is comprised of a 5 series oriented multiplexers, each shifting by a distance of 1, 2, 4, 8, 16 and 32 bits respectively. The barrel shifter also takes advantage of the fact that all bits between the bit length of the multiplexer stage and the 64^(th) bit are zero. As a result, no hardware is necessary to keep track of these bits. Thus, five series multiplexers having lengths of 33, 35, 39, 47 and 63 bits respectively can be employed having a reduced hardware footprint as compared to five 64-bit multiplexers or dual 32 bit multiplexers as are typically employed. Such a barrel shifter also permits rotation functions with minimal additional hardware logic.

At least one embodiment of the invention provides a barrel shifter comprising a 2N bit shifter having an upper N bit portion for receiving an N bit input and an lower N bit portion, wherein an X-bit right shift, X<N of a number yields an X bit right shift in the upper portion and an N-X bit left shift in the lower portion of the 2N bit barrel shifter, and further wherein N is an integer power of 2.

At least one other embodiment of the invention provides a 2N bit right only barrel shifter, where N is an integer multiple of 2. The 2N bit right only barrel shifter according to this embodiment may comprise a number of multiplexer stages corresponding to Log₂N, wherein each successive stage of the multiplexer adds 2^(x) additional bits to the number of bits in the preceding stage where x increments from 0 to (Log₂N-1).

An additional embodiment of the invention provides a method of performing a positive X bit right shift with a 2N bit right only shifter, 0<X<N, wherein X is an integer and N is a word length in bits. The method of performing a positive X bit right shift with a 2N bit right only shifter according to this embodiment may comprise receiving an N bit data input in an upper N bit portion of the shifter, shifting the input by X bits, and retrieving the results from the upper N bit portion of the 2N bit shifter.

Yet another embodiment of the invention provides a method of performing a negative X bit right shift with a 2N bit right only shifter, 0<X<N, wherein X is an integer and N is a word length in bits. The method of performing a negative X bit right shift with a 2N bit right only shifter according to this embodiment may comprise receiving an N bit data input in an upper N bit portion of the shifter, shifting the input by X bits, and retrieving the results from the lower N bit portion of the 2N bit shifter.

A further embodiment of the invention provides a method of performing a positive X bit left shift with a 2N bit right only shifter, 0<X<N wherein X is an integer and N is a word length in bits. The method of performing a positive X bit left shift with a 2N bit right only shifter according to this embodiment may comprise receiving an N bit data input in an upper N bit portion of the 2N bit right only shifter, determining a bit wise inverse of X, shifting the input by (1+inverse of X) bits, and retrieving the results from the lower N bit portion of the 2N bit shifter.

Still another embodiment of the invention provides a method of performing a negative X bit shift with a 2N bit right only shifter, 0<X<N wherein X is an integer and N is a word length in bits. The method of performing a negative X bit shift with a 2N bit right only shifter according to this embodiment may comprise receiving an N bit data input in an upper N bit portion of the 2N bit right only shifter, determining a bit wise inverse of X, shifting the input by (1+inverse of X) bits, and retrieving the results from the upper N bit portion of the 2N bit shifter.

Yet another additional embodiment of the invention provides a method of performing an X bit right rotation of an N bit number with a 2N bit right only barrel shifter where 0<X<N. The method of performing an X bit right rotation of an N bit number with a 2N bit right only barrel shifter according to this embodiment may comprise receiving an N bit data input in an upper N bit portion of the 2N bit barrel shifter, right shifting the N bit data input by X bits into the N bit barrel shifter, and performing a logical OR of the contents of the upper N bit portion and lower N bit portion of the 2N bit barrel shifter.

Still another additional embodiment of the invention provides a method of performing an X bit left rotation of an N bit number with a 2N bit right only barrel shifter where 0<X<N. The method of performing an X bit left rotation of an N bit number with a 2N bit right only barrel shifter may comprise receiving an N bit data input in an upper N bit portion of the 2N bit barrel shifter, determining a bit wise inverse of X, shifting the input by (1+inverse of X) bits, and performing a logical OR of the contents of the upper N bit portion and lower N bit portion of the 2N bit barrel shifter.

A further embodiment of the invention provides a 2N bit barrel shifter. The 2N bit barrel shifter according to this embodiment may comprise a pair of upper and lower N bit shifter portions, wherein an X bit right shift of an N bit number yields a X bit right shift in the upper N bit shifter portion and an N-X bit left shift in the lower N bit shifter portion.

Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating a conventional parallel right and left shifting 32-bit barrel shifter comprising five series multiplexers each;

FIG. 2 is a schematic diagram illustrating a 64-bit right shifting only barrel shifter capable of signed right or left binary shifts in accordance with at least one embodiment of this invention;

FIG. 3 is a table illustrating right and left positive and negative shifts as performed with the barrel shifter according to various embodiments of this invention;

FIG. 4 is a table showing the results of right and left positive and negative shifts for a given input as performed with the barrel shifter according to various embodiments of this invention;

FIG. 5 is a table illustrating the results of an 8 bit rotation performed with a barrel shifter according to various embodiments of this invention; and

FIG. 6 is a diagram illustrating the stages of a multiplexer-based barrel shifter according to various embodiments of this invention.

DETAILED DESCRIPTION OF THE DISCLOSURE

The following description is intended to convey a thorough understanding of the invention by providing specific embodiments and details involving various aspects of a new and useful microprocessor architecture. It is understood, however, that the invention is not limited to these specific embodiments and details, which are exemplary only. It further is understood that one possessing ordinary skill in the art, in light of known systems and methods, would appreciate the use of the invention for its intended purposes and benefits in any number of alternative embodiments, depending upon specific design and other needs.

Referring now to FIG. 2, an exemplary embodiment of an improved barrel shifter architecture is shown for a microprocessor, wherein a 64-bit right only shifter 200 can provide the same functionality as the conventional double 32-bit shifter 100 shown in FIG. 1, while having a reduced circuit complexity and reduced power consumption. If the 64-bit shifter 200 is configured as two side-by-side 32-bit shifters, the following principles may be exploited. Assume that the binary number (up to 32-bits) to be shifted resides in the left side of the 64-bit shifter, labeled A in FIG. 2. Now, when, for example, a two bit right shift operation is performed, the left half of the 64-bit result contains the number A shifted right by two bits, or in other words, the number A with the rightmost (least significant) bits (LSB) truncated off and two leading zeros appended to the front (most significant bit) (MSB). However, the right half of the 64-bit shifter contains the number A characterized by only bits 1 and 0 chopped off from A in the shift operation followed by 30 zeros. Thus, performing a 2-bit right shift to A in the left half of the 64-bit shifter results in a 30-bit left shift in the right half of the 64-bit register. As a result, bi-directional shifting is possible with a 64-bit, right only shifter.

The above behavior can be explained by two facts. Firstly, a left shift is equivalent to a right shift of the same number of bit positions but in the opposite direction and vice versa. In other words, a left shift is equivalent to a right shift of the same absolute shift distance but of the opposite sign. Secondly, by selecting the left half of the 64-bit result, an implicit shift distance of 32 is added to the actual number of bit positions shifted right. In the above example shown in FIG. 2, the 2-bit right shift can be viewed as a negative 2-bit left shift. Selecting the left half of the 64-bit result is equivalent to adding 32 to the shift distance of −2. Hence, it is equivalent to a left shift of 30 bit positions. Also, since a negative right shift is equivalent to a positive left shift of the same shift distance, a negative right shift of 30 bit positions can be obtained by selecting the left half of the result of the 64-bit shifter having performed a 2-bit right shift. Similarly, negative left shift of 2 bit positions is performed by selecting the right half of the above 64-bit result. That is, the 64-bit right only shifter can be used to compute left and right shifts of up to 32 bit positions in either the positive or the negative sense.

Another advantage of the barrel shifter illustrated in FIG. 2 is that because each multiplexer can only shift right by 1, 2, 4, 8 and 16 bits respectively and the left half of the input is always selected to be zero, the required length of each multiplexer need only be 33, 35, 39, 47 and 63-bits respectively. This is because the other bits are all zeros and can be left out of the hardware logic. This results in simplified design, reduction of chip area and reduced power consumption.

Referring now to FIG. 3, a table illustrating the way in which right and left positive and negative shifts are performed with the barrel shifter according to various embodiments of this invention is depicted. The table 300 in FIG. 3 shows that positive and negative right shifts, that is shift distance D>0 and D<0, are performed with the 64 bit barrel shifter according to various embodiments by taking the upper portion and lower portion of the shifter respectively after performing a shift of shift distance D. Also positive and negative left shifts are performed by taking the lower portion and upper portion of the shifter respectively after performing a shift of shift distance equal to the inverse of D+1. For right shifts, the specified shift distance is applied directly to the shifter. In the case of the 64 bit shifter 310 depicted in FIG. 3, the upper portion 310 u would be the upper 32 bits and the lower portion 310 l would be the lower 32 bits. Left directional positive and negative shifts are performed by taking the lower and upper portions respectively after shifting the negation or inverse of the shift distance plus one bit.

Referring now to FIG. 4, an example illustrating the results an eight bit shift according to the procedures set forth in the table 300 of FIG. 3 is illustrated. Taking the 32 bit hex number AABBCCDD as an input, the result of a positive right shift is simply 00AABBCC. The last eight bits of the input, DD, are truncated off by the shift operation. Likewise, two leading zeros are appended to the leading portion of the input. Thus, the result remaining in the upper portion 310 u of the 64 bit shifter 300 will be 00AABBCC. The lower portion 310 u will contain the number DD followed by six zeros. This is equivalent to a negative right shift of 24 bits or analogously, a left shift of 24 bits.

A positive left shift of eight bits is derived by shifting (ˆD)+1, where ˆD is the bitwise inverse of D, and taking the contents of the lower portion 310 u. Thus, in this case, D=8 or 01000 in binary. The inverse of this is 10111. Adding 1 yields 11000 or 24 in decimal. So performing a 24 bit right shift in the 64-bit right shifter yields BBCCDD00 in the lower 32 bit portion of the shifter. This is the same as if the input AABBCCDD had actually shifted left by 8 bits. Similarly, a negative left shift of 24 bit positions, that is D=−24 is accomplished by right shifting by the inverse of D plus 1 or 24 bits, and taking the contents of the upper portion 310 u, or 000000AA.

The 64-bit right only barrel shifter 200 of FIG. 2 can also be used to perform the rotation operation. The rotation of a 32-bit quantity can be obtained by combining the result of a left shift and a right shift. As an example, rotating a 32-bit quantity by two bit positions to the right can be implemented by combining the results of right shifting the quantity by two bit positions and that of left shifting the same quantity by 30 bit positions. As demonstrated above, these two shift results are available respectively as the right and left halves of the 64-bit right shifter. Hence the same underlying shifter design can be used to compute 32-bit rotation to the right. Rotation to the left can be supported similarly.

Referring now to FIG. 5, a table illustrating the results of an eight bit rotation to the right performed with a barrel shifter according to various embodiments of this invention. In order to perform an eight bit rotation using the 64 bit right only shifter according to various embodiments of this invention, a shift by eight bits is performed on the input. This will leave the results of an eight bit right shift in the upper portion and the results of a 24 bit left shit in the lower portion, 00AABBCC and DD000000 respectively. These two numbers are logically OR-ed together to yield DDAABBCC.

FIG. 6 is a diagram illustrating the stages of a multiplexer-based barrel shifter according to various embodiments of this invention. The diagram shows the input as a 32 bit number in the upper 32 bit portion of the 64 bit multiplexer 600. The multiplexer 600 shown in FIG. 6 is comprised of five stages. However, it should be appreciated that the principles set forth herein are applicable to barrel shifters of different lengths, for example, 128 bits, 256 bits, etc., where N is the instruction word length of the processor, the length of the barrel shifter is 2N and the number of multiplexer stages required is Log₂N.

With continued reference to FIG. 6, the first stage of the multiplexer performs a one bit shift and thus is 33 bits in length. The second stage performs a two bit shift and thus is 33+2 or 35 bits in length. The third stage performs a four bit shift and is thus 35+4 or 39 bits in length. The fourth stage performs an eight bit shift and is thus 39+8 or 47 bits in length. Finally, the fifth stage performs a 16 bit shift and is 47+16 or 63 bits in length. With this combination of stages a shift of any length from 1 to 32 bits can be performed using various possible combinations of the stages with a five bit control line having the most significant bit activating the fifth stage and the least significant bit activating the first stage. Furthermore, as compared to the prior art using dual parallel 32 bit shifters which requires 320 bits of multiplexer logic, the 64 bit right only barrel shifter in accordance with various embodiments of the invention requires only 217 bits of multiplexer logic. This is a logic savings of nearly 33% which will hold constant for differing word sizes, such as, for example, 16 bit, 32 bit, 64 bit, 128 bit, etc.

While the foregoing description includes many details and specificities, it is to be understood that these have been included for purposes of explanation only, and are not to be interpreted as limitations of the present invention. Many modifications to the embodiments described above can be made without departing from the spirit and scope of the invention. 

1. A barrel shifter comprising: a 2N bit shifter having an upper N bit portion for receiving an N bit input and a lower N bit portion, wherein an X-bit right shift, X<N of a number yields an X bit right shift in the upper portion and an N-X bit left shift in the lower portion of the 2N bit barrel shifter, and further wherein N is an integer power of
 2. 2. The barrel shifter according to claim 1, wherein the 2N bit shifter is a right direction only shifter.
 3. The barrel shifter according to claim 1, wherein an X bit rotation, X<N, of an input is achieved by a bit-wise logical OR of the contents of the upper N bit portion and lower N bit portion after performing an X bit right shift.
 4. The barrel shifter according to claim 1, wherein the 2N bit barrel shifter comprises a Log₂N stage multiplexer having Log₂N bit control line, wherein each bit of the control line is connected to a respective stage of the multiplexer.
 5. The barrel shifter according to claim 4, wherein N=32 and the multiplexer comprises 5 stages having 33-bits, 35-bits, 39-bits, 47-bits and 63-bits respectively.
 6. A 2N bit right only barrel shifter, where N is an integer multiple of 2, comprising: a number of multiplexer stages corresponding to Log₂N, wherein each successive stage of the multiplexer adds 2^(x) additional bits to the number of bits in the preceding stage where x increments from 0 to (Log₂N-1).
 7. The 2N bit right only barrel shifter according to claim 6, wherein, N=32, the first multiplexer stage is 33 bits, the second multiplexer stage is 35 bits, the third multiplexer stage is 39 bits, the fourth multiplexer stage is 47 bits and the fifth multiplexer stage is 63 bits, wherein the 5 stages are adapted to perform 1-bit, 2-bit, 4-bit, 8-bit and 16-bit shifts respectively.
 8. A method of performing a positive X bit right shift with a 2N bit right only shifter, 0<X<N, wherein X is an integer and N is a word length in bits, comprising: receiving an N bit data input in an upper N bit portion of the shifter; shifting the input by X bits; and retrieving the results from the upper N bit portion of the 2N bit shifter.
 9. A method of performing a negative X bit right shift with a 2N bit right only shifter, 0<X<N, wherein X is an integer and N is a word length in bits, comprising: receiving an N bit data input in an upper N bit portion of the shifter; shifting the input by X bits; and retrieving the results from the lower N bit portion of the 2N bit shifter.
 10. A method of performing a positive X bit left shift with a 2N bit right only shifter, 0<X<N wherein X is an integer and N is a word length in bits, comprising: receiving an N bit data input in an upper N bit portion of the 2N bit right only shifter; determining a bit wise inverse of X; shifting the input by (1+inverse of X) bits; and retrieving the results from the lower N bit portion of the 2N bit shifter.
 11. The method according to claim 10, wherein shifting comprises sending a Log₂N bit control signal to a Log₂N stage multiplexer.
 12. The method according to claim 11, wherein N=32, and the 5 stage multiplexer comprises 33-bit, 35-bit, 39-bit, 47-bit and 63-bit stages shifting 1 bit, 2 bits, 4 bits, 8 bits and 16 bits respectively.
 13. A method of performing a negative X bit shift with a 2N bit right only shifter, 0<X<N wherein X is an integer and N is a word length in bits, comprising: receiving an N bit data input in an upper N bit portion of the 2N bit right only shifter; determining a bit wise inverse of X; shifting the input by (1+inverse of X) bits; and retrieving the results from the upper N bit portion of the 2N bit shifter.
 14. The method according to claim 13, wherein shifting comprises sending a Log₂N bit control signal to a Log₂N stage multiplexer.
 15. The method according to claim 14, wherein N=32, and the 5 stage multiplexer comprises 33-bit, 35-bit, 39-bit, 47-bit and 63-bit stages shifting 1 bit, 2 bits, 4 bits, 8 bits and 16 bits respectively.
 16. A method of performing an X bit right rotation of an N bit number with a 2N bit right only barrel shifter where 0<X<N comprising: receiving an N bit data input in an upper N bit portion of the 2N bit barrel shifter; right shifting the N bit data input by X bits into the N bit barrel shifter; and performing a logical OR of the contents of the upper N bit portion and lower N bit portion of the 2N bit barrel shifter.
 17. A method of performing an X bit left rotation of an N bit number with a 2N bit right only barrel shifter where 0<X<N comprising: receiving an N bit data input in an upper N bit portion of the 2N bit barrel shifter; determining a bit wise inverse of X; shifting the input by (1+inverse of X) bits; and performing a logical OR of the contents of the upper N bit portion and lower N bit portion of the 2N bit barrel shifter.
 18. A 2N bit barrel shifter comprising: a pair of upper and lower N bit shifter portions, wherein an X bit right shift of an N bit number yields a X bit right shift in the upper N bit shifter portion and an N-X bit left shift in the lower N bit shifter portion. 